library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;  
use ieee.std_logic_arith.all;

entity regfile is
port (  ra1, ra2, wa3 	: in std_logic_vector(4 downto 0);
		clk, we3		: in std_logic;
		wd3				: in std_logic_vector(31 downto 0);
		rd1, rd2		: out std_logic_vector(31 downto 0));
end entity;

architecture regfile_arch of regfile is
	type memory is array (31 downto 0) of std_logic_vector(31 downto 0);
	signal mem : memory;
	begin
		process (we3, clk)
		begin
			rd1 <= mem(conv_integer(ra1));
			rd2 <= mem(conv_integer(ra2));
		
			if (we3 = '1' and clk = '1') then
				mem(conv_integer(wa3)) <= wd3;
			end if;
		end process;
end regfile_arch;
